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Wednesday, December 5 • 4:30pm - 5:00pm
Accelerating VNF Data Plane in FPGA Based P4-programmable Acceleration Card

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Network function virtualization is in full swing. Every day a purpose-built networking box is replaced by a software application running at commodity x86 hardware. Even the switch - a very basic network device now has its software counterpart, and it’s a very popular one! To further strengthen this trend, vendors bring FPGA based Programmable Acceleration Cards into the game. Programmable Acceleration Cards can augment the CPU performance in the data plane and improve single physical machine throughput. Since NFV is all about the ecosystem and collaboration, PACs (Programmable Acceleration cards) must be programmed and operated in a standard way. The P4 language and P4Runtime API, both being open standards backed by strong consortiums, has gained a lot of traction in this regard. P4-programmable Acceleration Cards run at network line rate and perform many of the compute-intensive per-packet tasks: encapsulation, decapsulation, ACLs, load balancing, statistics, cryptography, DPI, QoS, and others. All fully defined by network architect, not the hardware vendor. The great part is that P4-programmable Acceleration Cards still fully support virtualization. The same x86 server that was running vEPC yesterday is running vBNG/BRAS today and will run an application-aware load balancer tomorrow. Thanks to this full P4 programmability, FPGA-based Programmable Acceleration Cards are now a standard, commodity part of a server rather than single-purpose accelerators.

avatar for Petr Kastovsky

Petr Kastovsky

CEO, Netcope Technologies
Petr, as a former Linux kernel device driver programmer and a digital hardware designer, has a profound understanding of Netcope's products functioning. The key products that he helped to launch to the market are the world's first 100GE network card for PCI Express interface and P4... Read More →

Wednesday December 5, 2018 4:30pm - 5:00pm PST
Salon 1-2